1. Field of the Invention
The invention relates to a multi-channel memory apparatus, and more particularly to a multi-channel memory apparatus utilizing an efficient ECC encoding and decoding scheme.
2. Description of the Related Art
Mass storage devices may include a number of memory devices, such as NAND memory devices, NOR memory devices, phase change devices, magnetic media devices, optical storage, etc., that typically include single-channel (i.e., one per memory device) controllers. Such single channel device controllers typically include error correcting code (ECC) encoding and decoding just before the data is written to or read from the storage device.
ECC encoding typically produces so-called check bytes used to correct data errors resulting from data storage in the device when reading data out of the storage device. In each channel, if no error is detected during decoding, the channel presents a properly decoded data output. Alternatively, if an error is detected during decoding, the channel presents a decode Error Detection Code (EDC) error output.
Along with the increase in the amount of channels in the mass storage devices, an efficient ECC encoding and decoding scheme to protect data is highly required.